The clock pulse input to a flip-flop (or any digital logic circuit) is treated as an independent input to the device- it's kind of an external control signal. It's usually a square-wave periodic signal from an oscillator. The idea is to define when the transitions at the output should happen. The internal circuitry of a clocked flip-flop is such that the data (D or JK according to the type of flip-flop) only goes through to the output when the clock signal tells it to.
The specific behavior depends on the type of flip-flop. For ``statically-clocked'' or ``level-sensitive'' flip-flops, the output depends on whether the clock input is high or low. For ``edge-triggered'',``dynamically-clocked'' flip-flops, the output responds to the input only when the clock signal changes from 0 to 1 (for positive edge-triggered) or 1 to 0 (for negative edge-triggered) flip-flops.